| Thread | Last Post | Replies |
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| user experiences of Altium Designer? | 27 Feb 2006 22:20 GMT | 2 |
I'm seeking out a new PCB design package, and have been pointed to look at Altium Designer from someone in the group. On (digital!) paper, it looks excellent, ideal in fact. But I would like to hear from real users, as our current system
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| RF Simulation Troubles in PSPICE | 25 Feb 2006 01:31 GMT | 3 |
My group and I are currently working on a school project and are having some troubles. We can't currently find any models for the parts of a project that we are working on and were curious if it was possible to create the models based off of the datasheets? These are the parts
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| Designer Needs to Learn More. Where? | 24 Feb 2006 02:11 GMT | 1 |
I am a part time contract PCB designer. Not some giant corporation, just one guy doing boards when he can :-) Been at it for a long time, but I am not learning new skills, and so I am falling behind on multilayer design, as in 8+ layers with numerous split planes, as well
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| Where does the spice effort lie? | 21 Feb 2006 18:23 GMT | 11 |
Hi, I was wondering if anyone can help me figure out where the "effort" in a given Spice implementation lies, specifically 3fg. For example, I'm wondering how much total % effort (starting from knowing KCL and KVL) over the past 25 years was due to:
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| Assembler to PAP conversion ? | 21 Feb 2006 06:11 GMT | 1 |
is there any tool that allows - for example PIC Hex file - converting to a graphical program flow diagram ? Long time ago, I have lost my assembler code and it is very hard to
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| SDT 386+ | 21 Feb 2006 01:16 GMT | 16 |
Will Orcad SDT 3.22 or SDT 386 + run on a K5 computer if I can get a 5.25 floppy drive to function so that I could load the SDT3.21? Will I have to install some version of DOS to do this? I have versions of DOS that start at 3.3. or maybe earlier
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| How draw electrical drawings? | 20 Feb 2006 19:52 GMT | 6 |
Hope this is the right place for this questions: 1. When making drawings that use symbology such as electrical schematics for PLC and control circuits..... what SIZE should thee symbols be drawn at
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| Which is the best hobby do-it-yourself method for making PCB's? | 20 Feb 2006 10:49 GMT | 78 |
In the past I have been using the toner transfer iron on technique. The best I have gotten is 75-80% of the board done ... the remaining 20 - 30% is rework for missing/broken traces etc. I am just wondering what is the best hobby do-it-yourself method?
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| Can anyone help with these Spice models.......... | 16 Feb 2006 23:33 GMT | 5 |
Alreayd searched the net, without any result. Looking for Spice models of voltage regulators: LM317, LM329 and LM337. Any help is appreciated.
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| simple ngSPICE simulation headache | 16 Feb 2006 10:40 GMT | 8 |
Arrrggghhh....I'm at a loss as to the source of these errors. I get them with the most basic circuit. My tools: gEDA suite version from Jan 2006: gschem -> gnetlist -> ngspice.
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| PCB Layout and simulation using Tina 7? | 15 Feb 2006 15:08 GMT | 3 |
I purchased a low end simulation program from www.Tina.com (DesignSoft), and it seems to work pretty well, especially for a $30 package. I have been doing my major electrical and electronic designs with PADS-PCB and PADS-Logic, from Mentor Graphics, but they do not offer simulation
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| Altium DXP and Hex Inverter (Multipart ICs) | 15 Feb 2006 14:36 GMT | 3 |
With another schematics design program, when one chooses something like a CD4049 timer or its equivalent the program will lay down all parts. However, Protel DXP seems to klutz when it comes to this or am I doing something wrong? Also, the subparts of the libraries for such a
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| Cadence Allegro SBP15.5 - Exporting Gerbers | 14 Feb 2006 16:46 GMT | 1 |
When I export the Gerbers using the post-processer, I find that some layers are exported with incorrect information. After a little digging I realized that the contents of the layers listed in the post process settings spreadsheet do not correspond to
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| "Cool Touch" Soldering Tool | 13 Feb 2006 06:16 GMT | 3 |
Cold Heat Soldering Iron $19.99 plus s&H http://rapidresponse.directtrack.com/z/23560/CD2024/&dp=321031 ************************************
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| how to circumvent :"Convergence problem in transient analysis" | 10 Feb 2006 01:07 GMT | 4 |
Hi, I'm having that famous problem. Is there any way to cirumvent it (computing time, I have). Can anyone explain the reason for the error ? Can I go lower than the "minimum allowable step size" and what determines the "minimum allowable step size" anyway?
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