| Thread | Last Post | Replies |
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| saving schematic revisions in eagle? | 30 Dec 2005 01:55 GMT | 1 |
Is there anyway to (semi)automatically save revisions of schematics (and boards) in eagle? thanks - jim
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| Good, relatively low cost PCB layout SW? | 29 Dec 2005 02:01 GMT | 44 |
Someone had recommended PC123; a bit large for POTS but doable. BUT. It is impossible to get useable documentation. After a longwinded download, Adobe Acrobat reader complains that it
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| PSPICE 10.5 Communications Problems from Capture 10.5 | 23 Dec 2005 16:10 GMT | 4 |
After running some simple circuits within Capture/PSPICE 10.5, I get the OrCad's Capture cannot create a PSPICE netlist for the PSPICE engine to simulate. If you go into the Session Log, it days "Unable to initialize pspice explorer while creating netlist file." If you try to
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| spice libary problem | 23 Dec 2005 15:30 GMT | 1 |
I have added a library of Tube to Orcad 10.3. I have runned simulation of a my circuit that contain a part of tube library and I have error undefined subcircuit. I have added the library as global and now I have errors of node floating.
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| pspice orcad 9.1 (again) | 23 Dec 2005 04:22 GMT | 3 |
Is there anyway that I can use 'capture' to place RMS current 'markers' on the circuit? also can i get multiple y axis' automatically. what I'm having to do now is to setup the probe display to view what I need.... every time i do a simulation, which is quite laborious. In previous
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| PCB Signal integrity simulation | 22 Dec 2005 08:55 GMT | 2 |
Hi to all, Looking for PCB Signal integrity simulation software (Hyperlinks Equivalent). Thanks,
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| request info on RFID uhf reader module | 21 Dec 2005 08:36 GMT | 7 |
I'm trying to get info to realize a custom system. In particulary I need to find and buy a reader module with antenna to integrate in my project. The system need to read UHF passive tag (860-900MHz) (like
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| pspice orcad 9.1 | 20 Dec 2005 09:19 GMT | 9 |
how do i get a circuit into the 'simulation hierarchy'...if it isn't. many thx Danny
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| Kneading Bread is Like Making a Shinto Sword | 19 Dec 2005 15:19 GMT | 52 |
You have already mixed up the ingredients... including the yeast. In order for your yeast to go yum yum on what it might find it needs some oxygen to eat it and convert things to carbon dioxide plus babys. Kneading introduces the atmosphere(with oxygen) to your dough.
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| primary currents in pspice 9.1 | 18 Dec 2005 21:46 GMT | 2 |
primary 0.01ohm and 10mH, secondary 40000mH. secondary connected to different rectifier types. in every damn case the voltages are exactly as predicted. what i can't understand is why the primary current dc value tendes to rise to ridiculous values of kAmperes over the
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| electrical interface problem | 16 Dec 2005 21:43 GMT | 35 |
I'm currently working on a board design and I have to interface two VLSI chips to each other that don't have exactly compatible level characteristics. To be more precise I have a differential CML output of U(t) = 1.8V +/- 0.400V * rect(t) being terminated 50 Ohm to Vref and a
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| Xilinx' encrypted HPICE models in PSPICE | 15 Dec 2005 18:56 GMT | 3 |
Hi community, I got a problem you might be able to assist me in solving. I downloaded several HSPICE models for the Xilinx Virtex-II Pro FPGAs from the Xilinx homepage. They are stored in a format I don't know: *.inc. The included
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| CAD software for IC Design | 12 Dec 2005 17:33 GMT | 1 |
I was wondering which CAD IC design software packages were popular within the market place? I've been using Altera Quartus II and know of Protel but which packages have the best reputation and therefore are the most popular?
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| Memory modeling in Liberty. | 12 Dec 2005 16:58 GMT | 2 |
Can someone please tell how RAW/WAW dependencies in a memory are modeled in Liberty? Thanx, Abhi.
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| help needed for parametric sweep | 12 Dec 2005 14:44 GMT | 1 |
I use Orcad (capture 9.2). I designed a circuit with VSIN as the source. I want to see the result of some parameters by changing the amplitude of the VSIN (Vi in my circuit). I need to use parametric sweep. How I can define the sweep variable? If I use VDC in place of
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