| Thread | Last Post | Replies |
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| Pads Ascii File Format | 31 Mar 2005 18:31 GMT | 2 |
Does anyone have a document that described the Pads Ascii file format? I am a Protel user trying to import a large Pads PowerPCB V3.5 Ascii file. It imports 99% correctly, all except the split planes. If I understood the Pads Ascii data a little better (particularly the x and
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| Problems with SPICE models from vendors | 31 Mar 2005 16:55 GMT | 37 |
The LM324 model from TI works fine,but the one from National Semiconductor is junk. I tried numerous Analog Devices models for various rail-to-rail opamps, and found that almost all i tried gave me the same kind of
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| BGA-272 and double side PCB | 31 Mar 2005 09:32 GMT | 4 |
I want to ask a question: I am doing a project which needs a DSP chip with BGA package. It has 272 pins. Is double layer PCB enough for routing? Thanks!
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| SuperSpice and .NODESET | 29 Mar 2005 11:56 GMT | 1 |
What is the easiest way to set initial node values with .NODESET command in SuperSpice? As I understand default initial guess is 0 Volts for all nodes; can that be changed to, say, 60V for all nodes? Can it be done within .subckt so that all +pins of all subcircuit of
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| SuperSpice and new component | 26 Mar 2005 06:22 GMT | 51 |
I need to analyse VERY simple circuit with SuperSpice (or should I use some other program?). Schematics has some resistors and 'special type' of (coax)amplifiers. All that I know about those amplifiers is that their U*I=22,5Watt, but that should be all that I need. It is connected
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| BGA pin coordinate | 25 Mar 2005 21:37 GMT | 2 |
In Pads Logic, how to define a component with BGA pins? For BGA package, the pin numbers are defined as A1, A2,... A9; B1, B2,... B9;
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| Yahoo group for FreePCB, open source PCB layout | 25 Mar 2005 12:23 GMT | 1 |
I could not find much info on users of FreePCB, so I started a Yahoo group. FreePCB is an open source program for PCB layout. It works with a PADSPCB netlist from any schematic package. http://groups.yahoo.com/group/FreePCB/
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| SPICE on entered schamatic(s) | 25 Mar 2005 00:36 GMT | 10 |
Any cheap systems that does that? With (relatively) modern op-amps?
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| SuperSpice .subckt and variable | 24 Mar 2005 15:40 GMT | 1 |
I want my subcircuit to have variable/parameter/value. Something like every resistor has resistance.. So, when I draw schematics, its very easy to change resistor value and each and every resistor can have different value. I want that same thing for my .subckt and not to have
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| BOM creation in PCAD | 24 Mar 2005 02:00 GMT | 1 |
BOM creation in PCAD seems really weird. It doesnt group all the same component types in the same row in the BOM. eg. if R1,R2,R3 are all the same type and value, they should occur in a
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| How to Rename a sheet in ViewDraw (DxDesigner 2.0)? | 23 Mar 2005 13:13 GMT | 1 |
I am not able to find out how to rename a sheet in a particular schematic. I can change the name of the schematic but not able to change the name of the sheet. Thanks Mohit
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| Protel netlist outputs | 21 Mar 2005 10:58 GMT | 9 |
My boss wants to proof circuits with component/net netlists in a condensed readable fashion, however Protel 2004 only produces one, as far as I can see, and he doesn't like the format. Can I generate a different ascii netlist format?
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| How important are chamfered routes? | 21 Mar 2005 06:31 GMT | 5 |
I was once told by a professional layout person that leaving a 90 degree inside corner on intersections of traces and/or pads was not good. Seems the acid is harder to wash out of the little corners and can result in over etching. I have seen tons of boards that don't
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| What is correct method? | 19 Mar 2005 22:13 GMT | 4 |
For general reference, if there is an instance where certain mounting holes should be part of a chassis ground net, is it proper to give them a part number and include them in the schematic, or is it ok to just electrically connect them on the PCB side with no record of them
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| Via pads in mid-layers | 19 Mar 2005 22:09 GMT | 7 |
In a multi-layer pcb, if I have a via going from the top layer to the bottom layer, is it necessary to have a full pad on the inner layers, or just on the layers where there is a connection to the via? For higher density cards, reducing or removing the anular ring in inner layers ...
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