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Electronics Forum / CAD / July 2005SOT23 pin numbering
What is the current convention with respect to pin numbers on SOT23? I have seen: Zetex 1 ===== 3 2 Then OnSemi 3 ===== 1 2 And Infineon (also in an older Siemens data book) 3 ===== 2 1 Somehow that looks like an invitation to a huge mess. What gives? Which one is now "standard"? Regards, Joerg http://www.analogconsultants.com Joerg, Yeah you are right, I don't know that there is one and only one standard in theory but there certainly isn't in practice. Typically what I and others I know do is decide on one company standard for SOT23 pin numbering and then stick to it. You may even cover it in a note on your assembly drawings and schematics so that there is no confusion down the road when someone sees a schematic symbol that doesn't match the manufacturer's pin numbering. FYI, I standardize on: 3 ==== 1 2 In my experience that one covers 80 - 90% of the manufacturer's devices I have ever used. That said, my present employer standardized long before I arrived on: 1 ==== 2 3  SignatureSincerely, Brad Velander > What is the current convention with respect to pin numbers on SOT23? > [quoted text clipped - 20 lines] > > http://www.analogconsultants.com Hello Brad, > Yeah you are right, I don't know that there is one and only > one standard in theory but there certainly isn't in practice. [quoted text clipped - 12 lines] > In my experience that one covers 80 - 90% of the > manufacturer's devices I have ever used. Same here, but the picture changes for European parts. I wonder what IPC and all this bureaucracy is good for when their can't even push through a standard for the pinout of a simple transistor case. Regards, Joerg http://www.analogconsultants.com Joerg, I also found that the parts specific to the RF and microwave worlds varied a lot more than the general jelly-bean variety transistors. I don't think you can blame the IPC, maybe Jedec or IEEE (and other packaging standards) but not the IPC. As far as I have ever seen, the IPC doesn't spec packages. Only how to deal with them in PCB design and assembly. SignatureSincerely, Brad Velander > Hello Brad, > [quoted text clipped - 5 lines] > > http://www.analogconsultants.com Hello Brad, > I also found that the parts specific to the RF and microwave > worlds varied a lot more than the general jelly-bean variety > transistors. The topper was when I found that the pin numbers on the SOT package of the same (!) device changed from a Siemens data book to the Infineon spec. Yet Infineon is the former Siemens semiconductor branch. That blew my mind. It was for the BAV99, pins 1 and 2 reversed. When you accidentally swap pins 1 and 2 because of such a mess and use lots of BAV99 as VCC/GND input clamps this will result in an impressive plume of smoke upon power-up. A meter usually won't show a short because of the two diode drops. > I don't think you can blame the IPC, maybe Jedec or IEEE (and > other packaging standards) but not the IPC. As far as I have ever > seen, the IPC doesn't spec packages. Only how to deal with them > in PCB design and assembly. I don't want to blame anyone. But I do expect standard bodies to work together and not do the "oh, it's not our turf" thing. In the same way that my clients expect me to work together with whomever is their layouter. Regards, Joerg http://www.analogconsultants.com > What is the current convention with respect to pin numbers on SOT23? Why number at all? Name them ebc, gsd or whatever, and hide the numbers on the schematic. If it's going to be critical for the techies, print the names on the silkscreen or on a diagram in a maintenance document. They seem to be pretty standard in SOT23- have I missed the odd men out? And why did we end up with such a mess with TO92s, where even the same numbered part can have variant pinouts? Paul Burke Hello Paul, > Why number at all? Name them ebc, gsd or whatever, and hide the numbers > on the schematic. If it's going to be critical for the techies, print > the names on the silkscreen or on a diagram in a maintenance document. That is ok if you do your own layout. But send it off like is customary and the CAD system of the layouter will pick whatever is its SOT23 variant. Worst case you have a major disaster when the board comes back. That is one reason why I am hesitant to base this data exchange on netlists. If the layouter doesn't use the same CAD he or she usually has to re-generate the whole schematic. Sad, but it prevents pin-out disasters. Regards, Joerg http://www.analogconsultants.com Joerg, If your PCB Designer has to re-enter anything then they are responsible for ensuring their version matches yours. So that is not really a valid concern. Like I said, a simple note in the schematic would suitably put them on notice as to your numbering convention. If they re-enter the works then they can use any convention that they want but it is their responsibility to match your overall netlist. Using the EBC, GSD, etc. is also fine but myself I hate that system. Can't say why other than some CAD systems don't support it or don't support it nicely. It also means that you do have to maintain a number of identical (physically) footprints. There again is one of my pet peeves, my current employer requires each company part number to have a unique footprint identified by the company part number. What a maintenance nightmare (should I call it an opportunity? Or maybe job insurance, since there is always library maintenance to do?). SignatureSincerely, Brad Velander > Hello Paul, > [quoted text clipped - 12 lines] > > http://www.analogconsultants.com Hello Brad, > If your PCB Designer has to re-enter anything then they are > responsible for ensuring their version matches yours. So that is > not really a valid concern. ... That's not quite how I see it. My clients are the main concern. They are my clients as well as the layouter's clients. So together we have to make sure that things pan out nicely. A blame game later helps nobody. > ....Like I said, a simple note in the > schematic would suitably put them on notice as to your numbering > convention. If they re-enter the works then they can use any > convention that they want but it is their responsibility to match > your overall netlist. Which brings up the point that you have to re-generate all the library parts or at least check them one by one. I am using Eagle but it was similar in others: You can find SOT23 and other packages with various pin numbering schemes among library files. > Using the EBC, GSD, etc. is also fine but myself I hate that > system. Can't say why other than some CAD systems don't support [quoted text clipped - 5 lines] > it an opportunity? Or maybe job insurance, since there is always > library maintenance to do?). CAD systems usually do not support EBC. They support 123. Or sometimes 321. The next day you pick another part and it may be 312. So I understand your employer very well. They want to avoid a major pitfall. In some more heavily regulated environments it goes further. Being that specific is law there. Regards, Joerg http://www.analogconsultants.com Joerg, Ok, saying it was not a concern may have been less than an ideal way to word it. But when you consider that they 'may' edit anything that you gave them because of particular issues with their CAD system or the manner in which they prefer to work, it becomes their responsibility by default. Your comment about libraries brings me to one point that I am adamant about, don't trust canned libraries. At best use them as a starting point but thoroughly check every part that you take from them. I suggest taking those parts out to a separate library such that you can remain very clear on which parts have been checked thoroughly. Usually by the time the parts have been properly checked, you could have made them from scratch just as quickly. If you don't believe me just consider what you must do to thoroughly check them? What do you need to do when creating them from scratch? Not much difference is there? The actual creation/drawing/placing time is far less than the detailed measures and calculating the land pattern geometry. SignatureSincerely, Brad Velander > Hello Brad, > [quoted text clipped - 16 lines] > > http://www.analogconsultants.com >don't trust canned libraries. Amen, amen, amen and amen. Especially Easy PC's, which shows all the symptoms of having been made by an unsupervised bored student on an ill-paid summer job. > Usually by the time the parts have been properly checked, you > could have made them from scratch just as quickly. Especially if you take into account the need for different footprints for different manufacturing technologies etc. Paul Burke Hello Brad, > Usually by the time the parts have been properly checked, you > could have made them from scratch just as quickly. If you don't > believe me just consider what you must do to thoroughly check > them? What do you need to do when creating them from scratch? Not > much difference is there? The actual creation/drawing/placing > time is far less than the detailed measures and calculating the > land pattern geometry. In Eagle a creation from scratch takes a lot of time, more than it did for me in OrCad. But there are easy ways to check things out: Place all the components you want to use or where you suspect irregularities on a schematic. Connect them in a way that allows easy identification where drain, source etc. should be. Switch to "PCB", scatter them on there, hit "autoroute" and print it all out. Magnify, so you have an easier time to measure against mfg pattern specs. That all takes just a few minutes but then you know whether the dimensions are right, pinout is correct etc. Of course, this is only time efficient if you use an integrated schematic/layout software. Regards, Joerg http://www.analogconsultants.com > Hello Brad, > > > Usually by the time the parts have been properly checked, you > > could have made them from scratch just as quickly. If you don't > > believe me just consider what you must do to thoroughly check [quoted text clipped - 4 lines] > > In Eagle a creation from scratch takes a lot of time, more than it did > for me in OrCad. But there are easy ways to check things out: Place all > the components you want to use or where you suspect irregularities on a > schematic. Connect them in a way that allows easy identification where > drain, source etc. should be. Switch to "PCB", scatter them on there, > hit "autoroute" and print it all out. Magnify, so you have an easier > time to measure against mfg pattern specs. > > That all takes just a few minutes but then you know whether the > dimensions are right, pinout is correct etc. Of course, this is only > time efficient if you use an integrated schematic/layout software. > > Regards, Joerg > > http://www.analogconsultants.com To answer your original question, there is no standard. I have done what others have suggested and created multiple footprints called SOT23, SOT23B, SOT23C It is a huge error-prone mess. Every SOT23 in a layout one needs to verified with a data sheet. > Why number at all? Name them ebc, gsd or whatever, and hide the numbers > on the schematic. The problem is that you then have to make a new footprint for every new schematic part -- something most people would prefer to avoid in the name of saving time! Hello Joel, > The problem is that you then have to make a new footprint for every new > schematic part -- something most people would prefer to avoid in the name of > saving time! Right now it is worse. Every good layouter will pull all the data books to see where what is. Else you'd receive a board, plug it in and kabloom. "Oh, but in my CAD package the top is pin 1...." Regards, Joerg http://www.analogconsultants.com >> Why number at all? Name them ebc, gsd or whatever, and hide the numbers >> on the schematic. > >The problem is that you then have to make a new footprint for every new >schematic part -- something most people would prefer to avoid in the name of >saving time! You don't have to do that. You just have to make a new footprint every time there is a different arrangement of pins. E E B B C C B C C B E C C E B E E B There are only six to make for the bipolars and then you can stop having to manually edit net-lists. If you have to lay out 6 PCBs with NPNs in them, there is sure to be a time savings. Signature-- kensmith@rahul.net forging knowledge > You don't have to do that. You just have to make a new footprint every > time there is a different arrangement of pins. [quoted text clipped - 5 lines] > to manually edit net-lists. If you have to lay out 6 PCBs with NPNs in > them, there is sure to be a time savings. In some CAD packages you don't even need to do that, you just need one schematic symbol with any pin order, one footprint symbol with any pin order then each part has references to the schematic, footprint and a table of what pins in the schematic symbol tie up with which pins in the footprint symbol just for that particular part. Hello James, > In some CAD packages you don't even need to do that, you just need one > schematic symbol with any pin order, one footprint symbol with any pin order > then each part has references to the schematic, footprint and a table of > what pins in the schematic symbol tie up with which pins in the footprint > symbol just for that particular part. Well, yes, that's how mine does it (Eagle). But when you send off to the layouters and they use another then you can only hope that they carefully read the notes since their CAD might assume another pin order on the package (footprint symbol). Regards, Joerg http://www.analogconsultants.com > Well, yes, that's how mine does it (Eagle). But when you send off to the > layouters and they use another then you can only hope that they carefully > read the notes since their CAD might assume another pin order on the > package (footprint symbol). Ah! I didn't realise you were using different schematic and layout tools. I've never been in that position myself but I see where your coming from now. James Hello James, >>Well, yes, that's how mine does it (Eagle). But when you send off to the >>layouters and they use another then you can only hope that they carefully [quoted text clipped - 4 lines] > I've never been in that position myself but I see where your coming from > now. We usually don't do layouts. If the layouters were to use Eagle as well things would be easier. But in the US most of them don't. Regards, Joerg http://www.analogconsultants.com > In some CAD packages you don't even need to do that, you just need one > schematic symbol with any pin order, one footprint symbol with any pin order > then each part has references to the schematic, footprint and a table of > what pins in the schematic symbol tie up with which pins in the footprint > symbol just for that particular part. That's what I meant. I sort of assumed tbat all PCB CADs were as rational as EasyPC. Now if only they'd put in proper back annotation and hierarchical schematics... Paul Burke Hello Paul, >> In some CAD packages you don't even need to do that, you just need one >> schematic symbol with any pin order, one footprint symbol with any pin [quoted text clipped - 4 lines] > That's what I meant. I sort of assumed tbat all PCB CADs were as > rational as EasyPC. Eagle is that rational, too. I really like it although the generation of new library parts is not nearly as easy and intuitive as it was in OrCad. > Now if only they'd put in proper back annotation and hierarchical > schematics... Back annotation, yes, but hierarchical schematics is one of the serious shortcomings of Eagle. OrCad had that from the beginning. Regards, Joerg http://www.analogconsultants.com > That's what I meant. I sort of assumed tbat all PCB CADs were as rational > as EasyPC. You assumed that all PCB CAD packages were as rational as EasyPC. I've previously used a high-end Mentor Graphics package - retailing for £50k PCB/£25k Schematic - that is not as rational and where you did have to create every combination (or would it be permutation?) of schematic/pcb pin number mapping. I suspect by the way the way library kept growing that the powers-that-were, controlling the standard company library, decided to create new symbols and footprints for every new part - what a waste! > Now if only they'd put in proper back annotation and hierarchical > schematics... At present I mainly use Pulsonix which is EasyPC's bigger cousin and has proper back annotation and hierarchical design. I guess WestDev/NumberOne Systems want to keep the two products separate because of their different markets and prices. James |
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