Electronics Forum / CAD / March 2005

   Ok, thanks for the clarification Simon. At first I thought
something was drastically different in DXP and I was unaware of
it. But they still will do a netlist, or I am betting that when
you do update PCB, you can still generate a report of the changes
being noted for the PCB. Same as I currently do with P99SE. After
reading in the netlist, you are essentially in the Update PCB
Synchronizer, with the list of changes on the screen, right click
on the list, generate a report of the changes. Some are always
non-circuit issues like Fiducials, test points or something else
that isn't found in a schematic.

   By the way, I cannot recall exactly what it is at the moment
but ERC checking has one very big hole that it doesn't check for
in Protel. Damn brain isn't working so well this morning but I
know there is one check that I would have them add in to make it
more complete, in the mean time it is not bad but only about 95%
complete. Maybe it has even been added into DXP already, aaahhh I
remember, checking for continuity and connection across ports and
netnames, also single node nets regardless of pin type and
whether you connected a wire and ran it to a port. Check that all
the names match and that there is at least one connection across
them if they exist. Still not foolproof though because there is
no way for it to know there should be X number of connections on
a net in total. OrCAD used to do a net or port name connectivity
dump, I used to use it to try and find slightly misspelled net or
port names because they would usually come up right close
together on the report. They also would show a listing of
netnames where you had connected dissimilar netnames together
intentionally.

   However, as far as Ivan's enquiry goes, check the Schematic
thoroughly, do the ERCs, update to the PCB, generate a report of
the synchronizer updates, have the boss sign off on the
schematic, the ERC check, then an update PCB change report and a
DRC report. At our shop the designers add notes to either the ERC
or the netlist/synchronizer report, indicating what the issues
are that generated any message. (i.e. The update report is trying
to delete a fiducial. we add a handwritten note stating that
"fiducials are not found in the schematic". Or, "Shorting
connection added to implement Star Point Ground", etc. )

   After all of this our design manager signs off on our designs
and keeps the design paperwork including these various checking
reports in a file cabinet. For too many years he had designers
telling him things were fine and dandy, now he holds this
paperwork over your head and if anything is wrong it had better
have been something that slipped through the checking without
being caught for some reason. Then we adapt our checking and
check lists to cover any new found issues. If you touched the
board after the checks and cause any problems, he will have you
by the short and curlies. He is not a nice guy but so far I
managed to stay on his good side, others have not and I see how
they are treated by him. I just plain don't want to be there, I
don't need that aggravation in my life.