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Electronics Forum / CAD / February 2005Power-On Reset
I need a power-on reset that lasts around 5ms. Process is CMOS 1.65V < VDD < 5.5V Components available besides CMOS: Lateral PNP Vertical PNP Caps up to 20pF Resistors up to 1Meg Suggestions? ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. > Suggestions? Many of the recent Microchip PIC power-on-resets use a digital counter internally. I'm guessing that they're working within confines similar to what you have and also they're trying to keep power consumption while asleep to a minimum and deal with brownout recovery. I don't know the details but they must be taking on-chip clock in the 10's or 100's of kHz to tick everything along. What requirements do you have regarding power consumption while asleep, brownout recovery, ? Tim. >> Suggestions? > [quoted text clipped - 9 lines] > >Tim. This dude doesn't sleep, but power consumption is critical. (Hearing-aid-related is all I can say right now.) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. Well the funniest post was one suggesting that I work at Maxim, seeing as how I just spent over 3 years at National Semi and that I consider Maxim to be a despicable company (although they do have a few nice parts, if you can get ever get them). I guess I was trying to say that the existence of an entire product line at Maxim suggests this function is one worth paying for. The fellow who posted (correctly) that I didn't even mention switch bounce was right on the money as to why a cap and resistor can get you into trouble. Of course if the chip at least has POR circuitry and a POR reset pin then the cap and resistor may be fine, as long as the datasheet says so. Similarly I was not very clear about the process used-- I never meant to say you need an analog process. I am just saying the circuit needs to be designed at the transistor level. Digital simulators can be as simple as on/off indication with a little timing thrown in. That just is not enough when the power rails are all over that place. No, there are plenty of fine POR circuits done in CMOS for digital. If JT has a circuit that he can vary process corners it looks like he understands the grief of doing a POR. I have worked with a lot of digital guys that just can't comprehend that gate-level SPICE just does not work when the rails are at 1.7 volts. Heck, Bob Pease would say that analog SPICE doesn't work much better (;^o)- Hot-swap circuits are equally non-trivial. Did the card get stuck in for a millisecond, then yanked out, then stuck back in-- what is the state of all the circuits on both the mother and daughtercard.. ect ect ect Paul >>Suggestions? > [quoted text clipped - 9 lines] > > Tim. [snip] >If JT has a circuit that he can vary process corners it looks like he >understands the grief of doing a POR. I've been thru MUCH grief in my design lifetime, that's why I'm cautious as hell. >I have worked with a lot of >digital guys that just can't comprehend that gate-level SPICE just >does not work when the rails are at 1.7 volts. Digital guys are amusing, aren't they ?:-) >Heck, Bob Pease would >say that analog SPICE doesn't work much better (;^o)- I think Bob is becoming over-exaggerative in his old age. Picks absurd examples. Must be running out of material for his column. (Of course I'm a young man compared to Bob. He graduated MIT in 1961, I graduated MIT in 1962 :-) >Hot-swap circuits are equally non-trivial. Did the card get stuck >in for a millisecond, then yanked out, then stuck back in-- what is >the state of all the circuits on both the mother and daughtercard.. >ect ect ect > >Paul [snip] My application isn't hot-swap, but it's similar... even has a charge-pump, which turned out to be helpful in making the POR timing ;-) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. > [snip] > > [quoted text clipped - 9 lines] > > Digital guys are amusing, aren't they ?:-) I guess we are (but the bank and the boss enjoy the humor). At least my stuff goes *poof* with the rails at 1.7V, so using spice isn't all that interesting at 1.7V. ;-) > >Heck, Bob Pease would > >say that analog SPICE doesn't work much better (;^o)- [quoted text clipped - 17 lines] > charge-pump, which turned out to be helpful in making the POR timing > ;-) Does your charge-pump operate with 1.7V rails? ;-) .25V?  SignatureKeith [snip] >> My application isn't hot-swap, but it's similar... even has a >> charge-pump, which turned out to be helpful in making the POR timing >> ;-) > >Does your charge-pump operate with 1.7V rails? ;-) .25V? The specification requires 1.65V <= VDD <= 5.5V, over process corners and -40°C to +105°C I PASS ;-) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. > [snip] >>> [quoted text clipped - 8 lines] > > I PASS ;-) Don't dislocate your shoulder. ;-p Cheers! Rich [...] >The specification requires 1.65V <= VDD <= 5.5V, over process corners >and -40°C to +105°C > >I PASS ;-) Many FPGA and CPLD circuits do not become sane until the supply voltage reaches and stays above some voltage. It would be nice if the power on reset chips also could be used to force the SELF-DESTRUCT signal to ground and the EXPLODE-IN-FLAMES/ signal near Vcc until after the RESET is over and then glitch free connect them to the signals from the CPLD. Signature-- kensmith@rahul.net forging knowledge > [snip] > >> [quoted text clipped - 8 lines] > > I PASS ;-) I chose .25V because one POR circuit requirement was for an active low to be guaranteed above a .25V VCC, until the power supply was within spec and stable for some period. Forcing a low voltage with a .25V rail, under worst case conditions, wasn't an easy thing to guarantee. SignatureKeith >> [snip] >> >> [quoted text clipped - 13 lines] >spec and stable for some period. Forcing a low voltage with a .25V >rail, under worst case conditions, wasn't an easy thing to guarantee. A low VTH N-Channel? My usual way is to generate a LOW for the region VTH < VDD < BG-Ref* plus a time-out. * BG-Ref = bandgap reference In this case I need a POR to last until the charge-pump has reached final value, WITHOUT loading the charge-pump with any current. If you think the obvious, you will guess my solution, but I can't confirm or deny it ;-) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. > >> [snip] > >> >> [quoted text clipped - 15 lines] > > A low VTH N-Channel? Well, it was 30 years ago, so no low Vt's. It wasn't my circuit, but IIRC Germanium NPNs were the only solution that worked, barely. (and what a PITA to get them approved, even then). ;-) > My usual way is to generate a LOW for the region VTH < VDD < BG-Ref* > plus a time-out. > > * BG-Ref = bandgap reference Seems reasonable. I guess with a 0Vt you should be able to get a decent POR circuit. > In this case I need a POR to last until the charge-pump has reached > final value, WITHOUT loading the charge-pump with any current. > > If you think the obvious, you will guess my solution, but I can't > confirm or deny it ;-) Well, I'm one of those humorous digital guys, so what do I know? ...but if I had to guess, I'd guess a mirror. SignatureKeith [snip] >> >I chose .25V because one POR circuit requirement was for an active low >> >to be guaranteed above a .25V VCC, until the power supply was within [quoted text clipped - 23 lines] >Well, I'm one of those humorous digital guys, so what do I know? ...but >if I had to guess, I'd guess a mirror. You forgot the smoke ;-) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. > [snip] >>> >I chose .25V because one POR circuit requirement was for an active low [quoted text clipped - 26 lines] > > You forgot the smoke ;-) Oh, no! We silly digital folk package our magic smoke on the inside too! SignatureKeith [...] >I chose .25V because one POR circuit requirement was for an active low >to be guaranteed above a .25V VCC, until the power supply was within >spec and stable for some period. Forcing a low voltage with a .25V >rail, under worst case conditions, wasn't an easy thing to guarantee. This sounds like a job for a JFET. Signature-- kensmith@rahul.net forging knowledge ... > Digital guys are amusing, aren't they ?:-) Why, thank you, Jim. That's one of the nicest things I've seen you write about me (and my kind ;-) ) in quite some time. :-) Cheers! Rich >I need a power-on reset that lasts around 5ms. > [quoted text clipped - 10 lines] > > Suggestions? Your favorite oscillator and a 20 bit counter. In the meantime you can continue work on that cap multiplier. Cheers, Harry Hello Harry, > Your favorite oscillator and a 20 bit counter. ... That is how I would do it, similar to a CD4060. It may not need 20 bits. That would depend on the trade-off between die area per pF for the oscillator capacitor and the real estate each divider occupies. It also depends on how small a current can safely be generated and used to charge and discharge that cap. 20pF seems pretty fat for a chip. Jim, maybe you can instead incorporate some nifty logic that holds down the reset until the charge pump has reached the desired voltage level, like x times battery level. Regards, Joerg http://www.analogconsultants.com >Hello Harry, > [quoted text clipped - 15 lines] > >http://www.analogconsultants.com I don't want to sense the CP output voltage. It's driving a capacitive transducer, and sensing will load it.. ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. Hello Jim, >I don't want to sense the CP output voltage. It's driving a >capacitive transducer, and sensing will load it.. > I don't know the architecture. But is there a way to sense and switch the divider path hi-Z when done sensing? Regards, Joerg http://www.analogconsultants.com >>Hello Harry, >> [quoted text clipped - 20 lines] > > ...Jim Thompson Even with a FET gate? Or is that a stupid question -- the closest I've been to IC design is that 4th-year class where you build an op-amp out of a CA3096 and a CA3086. SignatureTim Wescott Wescott Design Services http://www.wescottdesign.com >>>Hello Harry, >>> [quoted text clipped - 24 lines] >been to IC design is that 4th-year class where you build an op-amp out >of a CA3096 and a CA3086. The highest voltage on-chip is the pump output, so a FET gate needs a drain supply. ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. >>>>Hello Harry, >>>> [quoted text clipped - 29 lines] > > ...Jim Thompson And to think I'm charging folks for my time today -- good thing it's something I already know how to do. So you're back to an RC oscillator and a counter? SignatureTim Wescott Wescott Design Services http://www.wescottdesign.com >>>>>Hello Harry, >>>>> [quoted text clipped - 34 lines] > >So you're back to an RC oscillator and a counter? I'm contemplating a second pump with smaller capacitors as a counter... something like "CP-Style-Counter.pdf" on the S.E.D/Schematics page of my website. Since it would be ratiometric with the main pump I can use a sensor that's below VDD and thus powerable. ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. >I need a power-on reset that lasts around 5ms. > [quoted text clipped - 12 lines] > > ...Jim Thompson Why not just hold reset true as long as Vcc is below some level? John >>I need a power-on reset that lasts around 5ms. >> [quoted text clipped - 16 lines] > >John I need to time-out long enough that a charge-pump has reached maximum. Charge-pump is regulated by controlling input, has no load other than capacitance, so I can't sense CP voltage without disturbing things. ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. > I need a power-on reset that lasts around 5ms. > Process is CMOS [quoted text clipped - 4 lines] > Caps up to 20pF > Resistors up to 1Meg 50KHz relaxation osc, 8 bit counter, flip flop? There was an experimental thread here last year on CMOS flip flops that indicated that they could be 'guided' into the required POR state by pull up/down R's. That could maybe be the way to bring up the counter and flip flop in the Reset state. SignatureTony Williams. >I need a power-on reset that lasts around 5ms. > [quoted text clipped - 12 lines] > > ...Jim Thompson There are a lot of parts built in CMOS that do this, but very little on how they do it internally. Here's one (first made by Microchip or perhaps some company they bought): http://www.national.com/ds/MC/MCP809.pdf http://ww1.microchip.com/downloads/en/DeviceDoc/11194c.pdf It's basically what you want, except with a 200ms delay. In Microchips' block diagram they show a bandgap reference, a comparator and a delay circuit, just as you might expect. Similar non-stand-alone functions that people have designed into chips tend to be inferior to parts such as the above. Hopefully you can do better! Best regards, Spehro Pefhany Signature"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com > Similar non-stand-alone functions that people have > designed into chips tend to be inferior to parts > such as the above. I think that battery-operated consumer single-chip gizmos were using a similar (although probably no band-gap) technique back into the early 80's. At least that was the only way I could figure they were generating a power-on-reset delay of hundreds of ms. Some of these worked down below 1.2V. I never did figure out what magic they used internally (maybe related to, or even exactly the same as, Jim's mention of an internal charge pump?) Tim. POR circuits are NOT trivial to design. Many people have crashed and burned using latches, 555 timers and other schemes. This is why Maxim can get 50 cents for a reset chip. I have been told by very smart people that the only valid approach to a POR circuit is a transistor- level approach. You have to have fully characterized transistor models if you expect to SPICE it, macromodels will not do. Be sure to exercise the circuit (reality preferred to SPICE) for very slow as well as very fast power turn-on and over a range of temperatures and loads. This is really a design challenge so don't take it lightly. > POR circuits are NOT trivial to design. Many people > have crashed and burned using latches, 555 timers and [quoted text clipped - 7 lines] > over a range of temperatures and loads. This is really a > design challenge so don't take it lightly. What's wrong with a 1 uF cap from the POR pin to ground, with, say, a 10K pullup? Thanks, Rich >> POR circuits are NOT trivial to design. Many people >> have crashed and burned using latches, 555 timers and [quoted text clipped - 10 lines] >What's wrong with a 1 uF cap from the POR pin to ground, with, >say, a 10K pullup? Rich, I am unable to tell whether you were being sarcastic, or whether you really don't know why an RC circuit is a bad reset generator (in general). Commonly encountered supply waveforms that don't produce a reliable reset from the RC circuit: 1. A brief dip in the supply voltage that goes low enough to crash the processor, but it doesn't discharge the cap enough to cause a reset when the supply returns to normal. 2. Very slow dv/dt. The RC circuit will not assert reset. 3. The supply voltage sitting in a "brownout" state indefinitely. The RC circuit will not assert reset. A good reset generator will hold reset active for all values of supply voltage below some threshold all the way down to zero volts, regardless of dv/dt (except maybe for glitch filtering), and keep reset active for a certain period (some tens to hundreds of ms) after the voltage goes above the threshold. Regards, Allan [...] >A good reset generator will hold reset active for all values of supply >voltage below some threshold all the way down to zero volts, >regardless of dv/dt (except maybe for glitch filtering), and keep >reset active for a certain period (some tens to hundreds of ms) after >the voltage goes above the threshold. Actually, a good one will hold reset until a number of cycles of the system clock have gone by. Many parts must be clocked to reset correctly. Signature-- kensmith@rahul.net forging knowledge >[...] >>A good reset generator will hold reset active for all values of supply [quoted text clipped - 5 lines] >Actually, a good one will hold reset until a number of cycles of the >system clock have gone by. Many parts must be clocked to reset correctly. In my experience, ASICs that need reset to be active for a number of clocks will have logic to implement that function internally. The external reset signal will asynchronously reset two or three flip flops which are usually arranged as a shift register, and the output of this shift register is the synchronous reset for the rest of the chip. Even going back a quarter century, the Intel 8284 clock generator (for the 8086) had logic to synchronise the reset to the system clock and provide minimum pulse widths, etc. I can't help feeling that a reset chip that's designed on some analog process ('cause it needs accurate comparators and a reference) won't be very good at handling a system clock that's the better part of a GHz (as they are on my boards). If you have any counter-examples, please list them. I'm always willing to learn. Regards, Allan In article <76lm11h5etplekhmjph2rmtvvn9h3aubvn@4ax.com>, [...] >In my experience, ASICs that need reset to be active for a number of >clocks will have logic to implement that function internally. I guess you don't use the 8051. The Philips ones are he one example I can think of straight off the top where the reset must be held for N clock cycles. The Atmel ones seem to take it a step further. They get messed up if the reset double pulses on the assert edge. I think that must be something to do with the ISP functions. >Even going back a quarter century, the Intel 8284 clock generator (for >the 8086) had logic to synchronise the reset to the system clock and >provide minimum pulse widths, etc. So there's another example of a reset that needed to be held and synced. The fact that Intel provided the function on an external chip says something, I'm not sure what, about doing it inside the micro. Signature-- kensmith@rahul.net forging knowledge >In article <76lm11h5etplekhmjph2rmtvvn9h3aubvn@4ax.com>, >[...] [quoted text clipped - 6 lines] >up if the reset double pulses on the assert edge. I think that must be >something to do with the ISP functions. I have used 8051 variants in a number of products. They've always worked because the reset generator had a minimum pulse width that is greater than the oscillator start time. I take your point though: in an 8051 based design, it might be a good thing to keep it in reset until the oscillator starts, in case the crystal has unusual parameters and takes a long time to start. How would one go about making a 'crystal start' detector for an 8051? We don't want to load either of the xtal pins, and (IIRC) outputs like ALE won't be toggling while the reset is active. >>Even going back a quarter century, the Intel 8284 clock generator (for >>the 8086) had logic to synchronise the reset to the system clock and [quoted text clipped - 3 lines] >The fact that Intel provided the function on an external chip says >something, I'm not sure what, about doing it inside the micro. I think it says that in the days when 16000 transistors was a big chip, you should move as much stuff as possible off board. :) Regards, Allan [...] >How would one go about making a 'crystal start' detector for an 8051? >We don't want to load either of the xtal pins, and (IIRC) outputs like >ALE won't be toggling while the reset is active. I wasn't using the 8051's oscillator in the case where it was an issue. I just did the RESET logic inside a CPLD. It worked ok. Normally, the 8051s RC reset works fine. You can load the osc-out pin of the 8051 with a CMOS gate without causing serious trouble. CMOS gates have less capacitance than you normally hook to that node. >>So there's another example of a reset that needed to be held and synced. >>The fact that Intel provided the function on an external chip says >>something, I'm not sure what, about doing it inside the micro. > >I think it says that in the days when 16000 transistors was a big >chip, you should move as much stuff as possible off board. :) OR: It says that the CPU designer screwed up and they didn't want to turn the mask again. The 8080 had an instruction that was an almost 16 bit subtract. It didn't borrow correctly. I suspect that they changed the data sheet rather than fix a broken subtract. Signature-- kensmith@rahul.net forging knowledge > In article <76lm11h5etplekhmjph2rmtvvn9h3aubvn@4ax.com>, > [...] [quoted text clipped - 14 lines] > The fact that Intel provided the function on an external chip says > something, I'm not sure what, about doing it inside the micro. It says that Intel was staffed by idiots, or people who were so anxious to get _something_ working, that they jumped on the first design that actually shuttled data around, damn the clocking - full steam ahead! Thanks, Rich > On Tue, 22 Feb 2005 10:40:56 GMT, Rich Grise <richgrise@example.net> >>> over a range of temperatures and loads. This is really a [quoted text clipped - 6 lines] > you really don't know why an RC circuit is a bad reset generator (in > general). At the time, I was entirely serious. A cap and 10K pullup works just fine on, say, a 6502. I've been perusing the thread, and am slowly being dragged kicking and screaming into the 21st century. ;-) Thanks! Rich >At the time, I was entirely serious. A cap and 10K pullup works just >fine on, say, a 6502. I've been perusing the thread, and am slowly being >dragged kicking and screaming into the 21st century. ;-) It only works just fine some of the time- when you control the power on/off sequencing just so. If your 6502 is doing something critical, and especially if it's suppose to be running unattended 24/7 with no supervision you *need* a real reset circuit. Best regards, Spehro Pefhany Signature"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com >>At the time, I was entirely serious. A cap and 10K pullup works just >>fine on, say, a 6502. I've been perusing the thread, and am slowly being [quoted text clipped - 7 lines] >Best regards, >Spehro Pefhany I had a SMPS on a GenRad portable tester that I bragged couldn't be killed. So a smart-aleck came along and did a machine-gun staccato with the ON/OFF switch, and flame erupted ;-) So I fixed his a.s... I added some circuitry to the ON/OFF switch path that limited the recycle time to a safe value. ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. [...] >So a smart-aleck came along and did a machine-gun staccato with the >ON/OFF switch, and flame erupted ;-) I had the same problem without the smart-aleck. It was a bad contact in a customer supplied winch slip-ring assembly. It went open-connect-open at maybe 10Hz. I had to add a circuit that turned the power off if the current stopped. Signature-- kensmith@rahul.net forging knowledge > > POR circuits are NOT trivial to design. Many people > > have crashed and burned using latches, 555 timers and [quoted text clipped - 13 lines] > Thanks, > Rich If you ever had to troubleshoot equipment built that way you would never ask that question. The VTR interfaces for a video editing system at WACX in Orlando was designed for a reset generator chip, then they left out the chip and used a crappy R/C reset. The equipment worked when it was new but a couple years later it would only reset one out of 20 or more attempts. You could play around with the R/C values and make it work for a couple weeks, but they finally agreed to let me mod the equipment by stuffing the missing parts on the board and eliminated the problems. SignatureBeware of those who suffer from delusions of adequacy! Michael A. Terrell Central Florida ... >> > over a range of temperatures and loads. This is really a >> > design challenge so don't take it lightly. [quoted text clipped - 14 lines] > equipment by stuffing the missing parts on the board and eliminated the > problems. But notice the operative phrase here - "designed for a reset generator chip". That particular chip does, in fact, need a proper reset, as has been covered in other posts in the thread. I was talking about the kinds of chips that they made in the '80s, where there was a pin specifically designed to take a cap and R, and has a Schmitt trigger, and the whole chip is designed to get reset by that little circuit. But, as I've said in another post, I'm slowly being dragged, kicking and screaming, into the 21st century. ;-) Speaking of which, there was a family of "reset generator" chips once - did they fade away too? Thanks! Rich > But notice the operative phrase here - "designed for a reset generator > chip". That particular chip does, in fact, need a proper reset, as has [quoted text clipped - 13 lines] > Thanks! > Rich Rich, it was a 6502 which is not a recent part. It was popular in the early '80s. They also used the 6522 and several other chips I could swipe from an unwanted VIC-20 computer. In fact, I lifted the reset circuit from the VIC-20 service manual. SignatureBeware of those who suffer from delusions of adequacy! Michael A. Terrell Central Florida >POR circuits are NOT trivial to design. Many people >have crashed and burned using latches, 555 timers and [quoted text clipped - 4 lines] >transistor models if you expect to SPICE it, macromodels >will not do. I assume that these people were the same ones who would do this work. By any chance do you work for Maxim? There are quite a few chips (such as comparitors) that are well characterized at low voltages. You can often power parts of the reset circuit from the input side of the regulator to ensure that it gets powered before Vcc appears. If you want to be very sure of the Reset/ staying low during the supply upswing, you can use a JFET as the output switch. Some micro controllers have the reset circuit built in. If you follow the manufactures recomendations on most of those, the results are correct. The best and easiest way to do a brown out protection is to have the brown out comparitor turn off the main power. If the Vcc regulator is broken or the batteries too dead, this is the best thing to do. Running correct code to some random point and then restarting it over and over is no better than running bogus code. > Be sure to exercise the circuit (reality preferred >to SPICE) for very slow as well as very fast power turn-on and >over a range of temperatures and loads. This is really a >design challenge so don't take it lightly. Funny you didn't include the power switch bounce case and the brown out case in your suggested checks. These are more likely in real life. Signature-- kensmith@rahul.net forging knowledge >POR circuits are NOT trivial to design. Absolutely not, that's why I was asking. >Many people >have crashed and burned using latches, 555 timers and [quoted text clipped - 7 lines] >over a range of temperatures and loads. This is really a >design challenge so don't take it lightly. I'm at the device level. I've found a solution I can't divulge at the moment, maybe in two years, that tracks process corners and times relative to what needs the reset. ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. [...] >I've found a solution I can't divulge at the moment, maybe in two >years, that tracks process corners and times relative to what needs >the reset. Add a clock monitor input so that you are sure that the system clock is running before you drop the reset. I assume you are using a MEMS relay and dashpot so adding a stepper relay shouldn't be too hard. Signature-- kensmith@rahul.net forging knowledge >[...] >>I've found a solution I can't divulge at the moment, maybe in two [quoted text clipped - 6 lines] >I assume you are using a MEMS relay and dashpot so adding a stepper relay >shouldn't be too hard. ROTFLMAO ;-) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. >>[...] >>>I've found a solution I can't divulge at the moment, maybe in two [quoted text clipped - 8 lines] > > ROTFLMAO ;-) I wondered, "WTF MEMS???" so I looked it up. Sh*t man f*ck - it ain't that far from reality! Nanomachines! Buckytubes! The one-atom motor! Or is that a whole nother level of reality? Thanks, Rich >I wondered, "WTF MEMS???" so I looked it up. > [quoted text clipped - 5 lines] >Thanks, >Rich MEMS is already reality. AFAIUI, the first killer app was accelerometers for automotive air bags. Best regards, Spehro Pefhany Signature"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com >>I wondered, "WTF MEMS???" so I looked it up. >> [quoted text clipped - 11 lines] >Best regards, >Spehro Pefhany My circuit that needed the POR has a MEMS... can't say what however ;-) ...Jim Thompson | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food. >>>I wondered, "WTF MEMS???" so I looked it up. >>> [quoted text clipped - 16 lines] > > ...Jim Thompson Tease! Best regards, Spehro Pefhany Signature"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com > I wondered, "WTF MEMS???" so I looked it up. > [quoted text clipped - 5 lines] > Thanks, > Rich I assume you haven't seen the collections of MEMS images at: http://mems.sandia.gov/scripts/index.asp Take a look at their "image gallery" section at the bottom of the page for a group of micro photos of MEMS devices with some microscopic bugs included with for comparison. Or their "Gears and Transmissions" section for some lovely photos of microscopic gears and matching linkages. The "Movie section" is also good but I don't have a high speed connection for that. Robert [...] >I wondered, "WTF MEMS???" so I looked it up. > >Sh*t man f*ck - it ain't that far from reality! Nanomachines! Buckytubes! >The one-atom motor! > >Or is that a whole nother level of reality? We already have the electron-proton based M-G set so we have already passed the one atom point. Hint: Overhauser Signature-- kensmith@rahul.net forging knowledge > Similar non-stand-alone functions that people have > designed into chips tend to be inferior to parts > such as the above. I think that battery-operated consumer single-chip gizmos were using a similar (although probably no band-gap) technique back into the early 80's. At least that was the only way I could figure they were generating a power-on-reset delay of hundreds of ms. Some of these worked down below 1.2V. I never did figure out what magic they used internally (maybe related to, or even exactly the same as, Jim's mention of an internal charge pump?) Tim. |
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