Electronics Forum / Basics / March 2006

Hi all,

After I use Xilinx ISE do Place & Round and generate bit file, I am
confused with a DRC warning

"WARNING: DesignRules:7-Netcheck: An antenna was found on signal; this
means that a branch of this signal is partially routed or has a routing
stub".

I found bit file with this DRC warning cannot work properly.

But what's this signal connected to? A tri-state bus? Or this signal
wire form a loop?

Any suggestions will be appreciated!
Best regards,
Davy